1. Field of the Invention
The present invention relates to a semiconductor device with a built-in capacitor, and a method of manufacturing the same.
2. Description of the Related Art
During operation of a semiconductor device with a semiconductor chip, such as LSI (large-scale integration) chip, which is mounted on the substrate of the electronic device, the semiconductor chip may be electrically damaged due to the transient current produced during a switching operation of an internal circuit of the semiconductor chip.
For this reason, in the vicinity of the semiconductor device or the semiconductor chip, a capacitor (capacitive element) is inserted between the power supply terminal and the ground terminal, and this capacitor serves to absorb and accumulate (or bypass) the electric charge of the transient current in order to avoid the damage of the semiconductor device or the semiconductor chip. This capacitor is called a decoupling capacitor or a bypass capacitor.
On the other hand, when the internal circuits of the semiconductor chip are highly integrated and a high-frequency signal is used by the LSI, there is a possibility that the LSI malfunctions due to the switching noises (or noises resulting from changes of the power supply potential or the ground potential due to the transient current) occurring in the semiconductor package. Changes of the power supply potential due to the transient current may be called power supply bounce, and changes of the ground potential due to the transient current may be called ground bounce. In order to reduce the switching noises, the application of a decoupling capacitor is necessary.
FIG. 1 shows the composition of a ceramic package type semiconductor device as one of the conventional semiconductor devices having the decoupling capacitor mentioned above. For example, see Japanese Laid-Open Patent Application No. 05-335501 and Japanese Laid-Open Patent Application No. 11-031696.
As shown in FIG. 1, in the semiconductor device 30, a semiconductor chip 34 is accommodated in a cavity 33 which is formed by a ceramic substrate 31 and a cap 32. Among the external-connection terminals of the ceramic package, a ground terminal 35 and a power supply terminal 36 are respectively connected to a ground electrode 38 and a power-supply electrode 39 of the semiconductor chip 34 by wires 37, such as gold wires.
In the semiconductor device 30, conductor layers 42 and 43 with a dielectric layer 41 interposed between the conductor layers are disposed between the semiconductor chip 34 and the ceramic substrate 31. The conductor layer 42 is connected to a power supply terminal and the conductor layer 43 is connected to a ground terminal so that a decoupling capacitor 40 is formed.
In this manner, a decoupling capacitor with a comparatively large capacitance can be formed by disposing the capacitive elements between the semiconductor chip 34 and the ceramic substrate 31 in the vicinity of the semiconductor chip 34.
However, in the case of the ceramic package type semiconductor device mentioned above, it is difficult to take countermeasure against a large number of external-connection terminals of an LSI chip accompanied with high integration and advanced features of the LSI chip, and it does not fit miniaturization and weight saving of semiconductor device.
As one countermeasure against the large number of external-connection terminals of the LSI chip, the face-down bonding technique is utilized for mounting of a semiconductor chip. In the face-down bonding, the circuit formation surface of a semiconductor substrate is inverted as the bottom side surface. This technique is also called flip chip bonding.
FIG. 2 shows the composition of a decoupling capacitor provided in the face-down mounting type semiconductor device mentioned above. For example, see Japanese Laid-Open Patent Application No. 2002-170920.
As shown in FIG. 2, the semiconductor device 50 comprises a mounting substrate 51, and a first semiconductor chip 55 which is disposed on the mounting substrate 51 by connecting electrodes 54 of the first semiconductor chip 55 to electrode pads 52 of the mounting substrate 51 via solder balls 53.
The space (or clearance) is provided between the first semiconductor chip 55 and the mounting substrate 51, wherein no solder ball 53 is arranged, and a second semiconductor chip 57 incorporating a decoupling capacitor 56 is disposed in the space. In the second semiconductor chip 57, a signal wiring 58 is disposed at a location corresponding to the part where no solder ball 53 is arranged, and the signal wiring 58 is connected to the electrodes 54 of the first semiconductor chip 55.
In the case of the semiconductor device 50 shown in FIG. 2, it is necessary to arrange the second semiconductor chip 57, incorporating the decoupling capacitor, in the space of the first semiconductor chip 55 where no solder ball is arranged. Therefore, the size and form of the second semiconductor chip 57 will be restrained depending on the layout of the solder balls in the first semiconductor chip 55.
For this reason, it is necessary to customize the second semiconductor chip 57 for every model of the first semiconductor chip 55, which will cause the cost to increase. Moreover, a wafer process is needed preparation of the second semiconductor chip 57, which will cause the development period to increase.
On the other hand, as one countermeasure being taken against a large number of external-connection terminals of a semiconductor chip because of high integration and advanced features of the semiconductor chip as mentioned above, the structure in which the external connection terminals, such as solder balls, are arranged in an array formation is often utilized for the supporting substrate for supporting the semiconductor chip. The BGA (ball grid array) structure is commonly used as one of the above-mentioned structure.
FIG. 3 shows the composition of a conventional BGA type semiconductor device which incorporates a decoupling capacitor.
As shown in FIG. 3, the semiconductor device 70 comprises a supporting substrate (interposer) 73 wherein solder balls 72 are bonded to pads 71 that are arranged in an array formation on the back surface of the supporting substrate 73, and a semiconductor chip 75 which is disposed on the supporting substrate 73 and covered with an encapsulation resin 74.
The supporting substrate 73 is provided so that wiring layers are disposed on the surface and/or within the inside of an insulating substrate, such as glass epoxy. The surface wiring layer and the internal wiring layer are interconnected by interlayer-connection conductors, if needed.
Bonding pads 76 are disposed on the surface of the supporting substrate 73 and connected to a ground electrode 78 and a power-supply electrode 79 of the semiconductor chip 75 by wires 77.
In the above-mentioned semiconductor device 70, a conductor layer 81 and a conductor layer 82 with a dielectric layer 80 interposed between the conductor layers 81 and 82 are disposed between the semiconductor chip 75 and the supporting substrate 73. The conductor layer 81 is connected to the power supply terminal and the conductor layer 82 is connected to the ground terminal, so that a decoupling capacitor 83 is formed.
In this manner, a decoupling capacitor with a comparatively large capacitance can be formed by disposing the capacitor (capacitive elements) between the semiconductor chip 75 and the supporting substrate 73 near the location beneath the semiconductor chip 75.
However, in the case of the BGA type semiconductor device, it is necessary to connect the electrodes of the semiconductor chip to the electrodes/sockets of the electronic device through the bonding pads, the supporting substrate surface/internal layer wiring, and the external terminals (solder balls). If the conductor layer that is used as one electrode of the decoupling capacitor is formed on the supporting substrate 73, the conductor layer must have a comparatively wide area. For this reason, the space for arranging the wiring is limited. And, in order to secure the space for arranging the wiring, the size of the supporting substrate must be enlarged.
A conceivable technique for securing the space for arranging the wiring without changing the size of the supporting substrate 73 is to provide a multi-layer arrangement of the supporting substrate 73. However, the multilayer arrangement of the supporting substrate requires a complicated structure and it will cause the cost to increase.
Generally, the cost of a wiring substrate is equivalent to about 70 percent of the material cost of a semiconductor device package. It is desirable to avoid increase of the cost of a wiring substrate as much as possible.
In recent years, with miniaturization and high performance of electronic devices including a mobile phone and a PDA (personal digital assistant), there is the demand for further miniaturization and high performance of electronic parts, such as semiconductor devices carried on the electronic devices.
Not only the active component parts, such as semiconductor devices, but also the passive component parts, such as resistors, inductors, and capacitors, are carried on the electronic device. These passive component parts are needed for to stably operate the active component part like the semiconductor device, and they are disposed near or on the circumference of the semiconductor device on a wiring substrate (mother board) of the electronic device.
In order for further miniaturization of electronic devices, it is necessary to reduce the space for arranging the passive component parts as much as possible. Accordingly, reducing the occupation area of the capacitive elements, such as decoupling capacitors, as much as possible is also demanded.